Multiplexed pseudo noise pulse burst codes with space taper

ABSTRACT

A pulse signalling system combining a multiplexed pseudo-noise code expansion theory with a space-coded array antenna synthesis technique to produce a high resolution waveform. The antenna space coding technique enables the clearing of any desired area in the frequency portion of the ambiguity surface. The multiplexed code expansion process simultaneously controls the side lobes in the time domain by utilizing a pair of code signals which, upon detection, provide an impulse autocorrelation function.

United States Patent [1 1 Gutleber 1 MULTIPLEXED PSEUDO NOIE PULSE BURST CODES wrrn SPACE TAPER Frank S. Gutleber, 24 Carriage House Lane, Little Silver, NJ. 07739 [22] Filed: June 18, 1974 [21] App]. No.: 480,451

[76] Inventor:

'[ 51 Nov. 4, 1975 3,681,579 8/1972 Schweitzer H 178/69 R Primary Examiner-Benedict U, Safrourek Attorney, Agent, or FirmNathan Edelberg; Robert P.

Gibson; Daniel D. Sharp [57] ABSIRACT A pulse signalling system combining a multiplexed pseudo-noise code expansion theory with a spacecoded array antenna synthesis technique to produce a high resolution waveform. The antenna space coding technique enables the clearing of any desired area in the frequency portion of the ambiguity surface. The multiplexed code expansion process simultaneously controls the side lobes in the time domain by utilizing [56] References Cited f 0d 31 h d t HIT a pair 0 C Slgl'l S W 1C UPOT] C 101'1, PI'OVl e U ED STATES PATENTS an impulse autocorrelation function. 3,388,330 6/1968 Kretzmer 325/42 3,492,578 1/1970 Gerrish et a1. v. 325/42 5 Clams, 5 Drawing Figures 5$? ADDER ADDER ADDER 2 30 an DELAY 5 INVERTER ADDER DELAY 24 INVERTER ADDR DELAY 2 25 28 INVERTER ADDER DELAY Y 4o 34 mven'rzn MULTIPLEXED PSEUDO NOISE PULSE BURST CODES WITH SPACE TAPER The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalties thereon or therefor.

FIELD OF THE INVENTION This invention relates to pulse signalling systems and, more particularly, to such a system in which a high degree of resolution is simultaneously obtainable in both frequency and range. As will be understood, such characteristics are especially attractive in radar and navigation systems, altimeter and fuze applications, moving target indicators, and in communications systems, in general.

SUMMARY OF THE INVENTION The pulse signalling system of the present invention incorporates a multiplexed pseudo-noise code expansion theory, together with a space-coded array antenna synthesis technique similar to that described in my issued U.S. Pat. No. 3,130,410. The antenna space coding technique is formulated to surpress side lobes in the frequency domain of an ambiguity surface, whereas the multiplexed pseudo-noise code expansion theory is formulated to surpress side lobes in the time domain.

As will be seen below, a composite signal code structure is employed, consisting of a pair of signals tenned code mates, having amplitudes and autocorrelation functions which provide a peak output at a given time and a zero output (or outputs having the same magnitude but opposite polarity) at all other times. The individual bits, or elements, of the composite structure, furthermore, are controllably time spaced in position to clear a desired frequency area. The signal waveform recovered upon detection of such a radiated code structure will be seen to be an impulse function at the principal axis substantially simultaneously both in the time domain and in the frequency domain, independent of any doppler shift.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features of the present invention will be more clearly understood from a consideration of the following description taken in connection with the accompanying drawings in which:

FIGS. la-lf illustrate space coding and multiplexed pseudo-noise coding expansion theories helpful in an understanding of the present invention;

FIG. 2 shows a frequency response plot also helpful in an understanding of the invention.

FIGS. 3a and 3b are functional block diagrams of code generator and code pulse compression apparatus illustrating the invention; and

FIG. 4 is a series of pulse code representations as exist at various points within the block diagrams of FIG. 3.

DETAILED DESCRIPTION OF THE DRAWINGS m rr time displacement from the first code bit; and 2wn rf phase change introduced due to the doppler effect. If this code of expression (1) were applied to a matched filter of the type described in my issued US. Pat. Nos. 3,461,451, 3,519,746 or 3,634,765, for example, the phases of the code bits along the zero time axis would line up. The phase contribution of the doppler frequency in controlling the ambiguity function of a return along the frequency axis, therefore, is all that need be considered. In such case, the phases of the code bits become:

1 n, we n-W These expressions may be more generally written as:

n' l' I nI 11' (3) n' n-i- Letting rf K, expression (5) reduces to As will be seen, equation (6) is identical in fonn to equation (12) of my US. Pat. No. 3,130,410 and may be utilized in like manner to completely synthesize the time code structure for any desired lobe pattern along the frequency axis of the ambiguity surface. As with equation I2) there, equation 6) states that to form a new code bit position n we add the quantity %K to the previous code bit position n. Equation (6) thus indicates the basic method for building up the space-coded bit positions of this invention. Each time it is desired to extend the code, the number of bits will be doubled. Each added bit, furthermore, will be the distance Y2K from its own corresponding previous existent bit.

However, the quantity k can still be chosen in such a manner as to facilitate design procedures and to make as simple as possible the computations involved. For this reason, f, is defined as the doppler frequency where the first null in the frequency domain occurs. By making K equal to I at the first null, i.e. f equals f the entire design can be normalized. For K =f lf and by repeating equation (6) to find the time coded delays to produce forced nulls in the frequency domain for K, l, K, 3/2, K, 2, K, 5/2, the following 16 time code positions will be produced:

In order to normalize these'code positions along the time axes, the values in the above table are multiplied by 60 with the result being shown in FIG. la as the space-coded time positions for the code bits. As will be appreciated, this time position coding illustrates that forced nulls will appear in the frequency domain of the ambiguity surface when the first code bit is positioned at time 0, the second code bit is positioned at time 30, the third code bit is positioned at time 20, the fourth code bit is positioned at time 50, etc. This is also illustrated by the coded time position frequency response plot of FIG. 2 for different design values of K. The desired frequency area cleared of side lobes will be appreciated to extend from f, to f In general, because K f /f it can be shown that the maximum value of K of physical significance can be expressed as Blf where B is the signal bandwidth of the system. For f equal to 100 Hz, the desired frequency area cleared of side lobes in FIG. 2 will be seen to extend to 300 Hz, and 'r, the reciprocal of f at K I, will be seen to be l0,000 micro-seconds. a single, a

the

FIGS. lb and 1d show a pairof code signals termed code mates, having amplitudes and autocorrelation functions to compress to a single impulse lobelessly. As is described in my aforementioned U.S. Pat. Nos. 3,461,451, 3,519,746 or 3,634,765, when code mates of this type are detected and the resultant detected outputs are linearly added, there is provided an impulse output of high amplitude at a given time in a waveform and a zero output at all other times. Following the techniques described in such patents, the impulse autocorrelation functions for such code signals may be obtained, and are of the type respectively shown in FIGS. 1:- and 1e. The linear output for these detected code signals is shown in FIG. If as havinglasin-gle, high amplitude peak, completely free from spurious peaks of lower amplitude elsewhere in the wavefonn. As will be seen, the individual bits of these two code signals are inserted within the space-coded time positions of FIG. lathe high amplitude impulse output being developed-atnorrnalized"time position 77.

FIGS. 30 and 3b are functional block digarams showing-the generation of these code signal bits within the space-coded time positions, and the resulting detection and linear addition to provide the impulse output. In the discussion that follows, it will be understood that FIG. 3a illustrates the apparatus for generating the code signal bits for transmission, while FIG. 3b illustrates the apparatus for compressing the code signal bits received.

Thus; referring to FIG. 3a, a pulse generator providesa digitall signal to one input terminal of an adder l2 and to 'adelay 'circuit 14, which imparts a delay of Ar or 30, time positions to the generator outpin. The output of delay circuit I4 is coupled to a second input terminal of adder l2,and to an inverter 16. The signal from generator 10 and the output of inverter 16 are in turn coupled to another adder 18, whose output signal is applied to a second delay circuit 20. This circuit 20 imparts a delay of A1 or 20, time positions to the input code bits.

The output from delay circuit 20 is also seen to be applied to one input terminal of an adder 22 the other terminal of which is provided with the output from adder l2 and to a further inverter 24. The signal from the inverter 24 is applied to one input of yet another adder stage 26, also along with the output signal from adder 12. The otuput from adder 26 will then be seen to be applied to a third delay circuit 28, which imparts a delay of Ar or 15, code time positions. From delay circuit 28, the developed signal is applied both to an input terminal of a further adder stage 30 and to an inverter 32, the second input terminal of adder 30 being applied the output from adder 22.

The output signal from adder 22 is then applied to one input terminal of another adder 34, along with the output from inverter 32. The output signal from adder 34 is applied via a fourth delay circuit 36 first, to one input terminal of an adder 38 and second, to an inverter circuit 40. Also provided at the second input of adder 38 is the output signal from adder 30, the delay circuit 36 in this instant providing a delay of A1,, or 12, time code positions. The output from adder 38 is indicated by the reference notation 0,, whereas the output from inverter 40 is applied to an adder 42 along with the output from adder 30 to provide an output signal indicated as b,,.

The pulse code output signals developed by the adder stages l2, 18, 22, 26, 30, 34, 38 and 42 are shown in FIG. 4. The identities between the time spaced, pulse code signal from adder 38 and the time spaced signal code of FIG. lb as well as similar identities between the time spaced pulse code from adder 42 and the time spaced signal of FIG. 1d will be apparent.

The block diagram of FIG. 3b also includes a plurality of adder, delay and inverter circuits. As illustrated, the code signal represented by the notation a,, is radiated, for example, received with a doppler frequency shift, and applied as such to one input terminal of an adder 50, to another input of which the received, frequency shifted b, code signal is applied. That b signal code is also applied to an inverter 52, the output therefrom being applied to an adder 54 along with the a,, code.

The output signal from adder 50 is applied to a delay circuit 56, the imparted delay of which is equivalent to the A7 or 12, time code position delay of circuit 36 in the upper portion of the drawing. The output from delay circuit 56 is applied both to an input terminal of a further adder 58 and to an input terminal of another adder 62. The otuput signal from adder 54 is also applied first, to a second terminal of adder 58 and second, via an inverter 60 to the other input terminal of adder 62. The output signal from adder 58 is applied to a delay circuit 64, similar to the delay circuit 28, in imparting a delay of Ar;,, or [5, time code positions to the input pulse signal. As with the delay circuit 56, the output of circuit 64 is applied to a pair of adders, 66 and '70. The second input terminal of these two adders are respectively supplied with the output signal from adder 62 and with that signal inverted, as supplied from adder 62 via an intermediate inverter stage 68.

The output signal from adder 66 is, in turn, applied to a further delay circuit 72, similar to the delay circuit 20, in imparting a delay of An, or 20, time code positions to the individual pulse bits. The output of delay circuit 72 is applied both to an adder 74 and to an adder 78, other input terminals of which are respectively provided with the output pulse from the adder 70 and with an inverted pulse signal from that stage by means of an inverter 76. As shown, the output signal from adder 74 is finally applied via a delay circuit 80 to one input terminal of a last adder 82, to a signal input terminal of which is applied the output signal from adder 78. Delay circuit 80, in this regard, is similar to the delay circuit 14, in providing a delay of A1,, or 30, time code positions to the input pulse signal.

The pulse code output signals developed by the adder stages 50, 54, 58, 62, 66, 70, 74, 78 and 82 are also shown in FIG. 4. The output from adder 82 will be seen identical to the pulse code representation of FIG. If.

This illustrative example of FIGS. 1-4 thus shows that by transmitting a pair of coded signals, termed code mates, an impulse function can be obtained in the time domain of the ambiguity surface upon receipt and detection. By controlling the positions of a timing sequence into which the individual pulse bits are inserted, an impulse function can be obtained in the frequency domain substantially simultaneously therewith. Although a specific pair of code signals have been utilized, others of the type noted in my referenced patents may be employed as well, necessitating only a rearrangement of the adder and inverter positionings of FIGS. 3a and 3b to provide the continued impulse output in the time domain. With the same values selected for the design parameter K, the same doppler frequency area will continue to be cleared of side lobes in providing the high resolution return waveform. if a greater doppler frequency area were desired to be cleared, K can simply be increased from 5/2, to 3, to 7/2, etc., with the number of pulse bit positions in the timing sequence doubling for each increase. As such will be seen to correspondingly increase the complexity of the block diagram of FIG. 3, some compromise between resolution and construction would most likely be needed.

While there has been described what is considered to be a preferred embodiment of the present invention, it will be readily apparent to those skilled in the art that modifications may be made without departing from the scope of the teachings herein. It is therefore contemplated that the invention be read in light of the claims appended hereto.

I claim:

1. A pulse doppler frequency signalling system for generating a code mate pair of asymmetrically interleaved code bits for transmission and for reception after undergoing a doppler frequency shift which provides for code compression to a lobeless impulse function in the time domain and for controllable minimization of lobes in the frequency domain of the ambiguity diagram comprising a pulse generator for providing a single input pulse, and a code pair expander responsive to said input pulse and including a plurality of m cascaded code pair expansion circuits each doubling the number of code bits and thereby forming a new code mate pair, each of said code expansion circuits having circuit means for delaying the code bits of one of said previous code mate pairs and for adding the delayed previous code mate pair with the undelayed previous code mate pair to form a first expanded code, and each of said code expansion circuits having circuit element means for delaying and for inverting one of said previous code mate pairs and for adding the inverted delayed previous code mate pair to the undelayed previous code mate pair to form a second expanded code, the delay introduced into the delaying means of a given xth one of the m circuit means and circuit element means is given by W where f is the selected frequency of the xth null in the frequency domain.

2. The system of claim 1 further comprising a code pair compression means responsive to said generated first and second expanded codes, and including a plurality of m cascaded code pair compression circuits each halving the number of code bits and thereby forming a new code mate pair, said compression circuits each having delay means identical to the delaying means of the corresponding code pair expansion circuit and code inversion means for inverting one of the previous code mate pairs, and summing means for adding the code bits of the mth compression circuit to obtain a single output pulse.

3. The system of claim 1 wherein the xth code pair expander circuit includes a first portion for deriving the bits of the first code a, and a second portion for deriving the corresponding bits of the second code 17,, said first portion including means for delaying the previous code b, and adding the latter to the previous code a and said second portion including means for inverting the delayed code b and adding said delayed inverted code to the previous code a,

4. The system of claim 2 wherein the xth code pair expander circuit includes a first portion for deriving the bits of the first code a, and a second portion for deriving the corresponding bits of the second code b said first portion including means for delaying the previous code b and adding the latter to the previous code a, and said second portion including means for inverting the delayed code b and adding said delayed inverted code to the previous code a,

5. The system of claim 2 wherein the yth code pair compression circuit includes a first portion for deriving the bits of the first code a, and second portion for deriving the corresponding bits of the second code b said first portion including means for delaying the bits of the previous code a,, and adding these delayed bits to the bits of previous code b,, and said second portion including means for inverting the bits of the previous code b,, and said second portion including means for inverting the bits of the previous code b and adding these inverted bits to the delayed bits of previous code a,,

UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT Nb. 1 DATED If liovenii er 1975 |NVENTOR(S) I F au; S. Gqfleuer It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

The correct title is: Multiplexec't Pseudo Noise Pulse Burst Codes with Spa 0e Taper" Column 3, lines 28 and 29, delete "a single, a the".

Signed and scaled this thirteenth Day of April 1976 [SEAL] A nest:

RUTH C. MASON C. MARSHALL DANN Arresting Uffr'ver (nnmrr'ssr'mu-r u] Parents and Trademarks 

1. A pulse doppler frequency signalling system for generating a code mate pair of asymmetrically interleaved code bits for transmission and for reception after undergoing a doppler frequency shift which provides for code compression to a lobeless impulse function in the time domain and for controllable minimization of lobes in the frequency domain of the ambiguity diagram comprising a pulse generator for providing a single input pulse, and a code pair expander responsive to said input pulse and including a plurality of m cascaded code pair expansion circuits each doubling the number of code bits and thereby forming a new code mate pair, each of said code expansion circuits having circuit means for delaying the code bits of one of said previous code mate pairs and for adding the delayed previous code mate pair with the undelayed previous code mate pair to form a first expanded code, and each of said code expansion circuits having circuit element means for delaying and for inverting one of said previous code mate pairs and for adding the inverted delayed previous code mate pair to the undelayed previous code mate pair to form a second expanded code, the delay introduced into the delaying means of a given xth one of the m circuit means and circuit element means is given by 1/2 fd where fd is the selected frequency of the xth null in the frequency domain.
 2. The system of claim 1 further comprising a code pair compression means responsive to said generated first and second expanded codes, and including a plurality of m cascaded code pair compression circuits each halving the number of code bits and thereby forming a new code mate pair, said compression circuits each having delay means identical to the delaying means of the corresponding code pair expansion circuit and code inversion means for inverting one of the previous code mate pairs, and summing means for adding the code bits of the mth compression circuit to obtain a single output pulse.
 3. The system of claim 1 wherein the xth code pair expander circuit includes a first portion for deriVing the bits of the first code ax and a second portion for deriving the corresponding bits of the second code bx, said first portion including means for delaying the previous code bx 1 and adding the latter to the previous code ax 1, and said second portion including means for inverting the delayed code bx 1 and adding said delayed inverted code to the previous code ax
 1. 4. The system of claim 2 wherein the xth code pair expander circuit includes a first portion for deriving the bits of the first code ax and a second portion for deriving the corresponding bits of the second code bx, said first portion including means for delaying the previous code bx 1 and adding the latter to the previous code ax 1, and said second portion including means for inverting the delayed code bx 1 and adding said delayed inverted code to the previous code ax
 1. 5. The system of claim 2 wherein the yth code pair compression circuit includes a first portion for deriving the bits of the first code ay and second portion for deriving the corresponding bits of the second code by, said first portion including means for delaying the bits of the previous code ay 1 and adding these delayed bits to the bits of previous code by 1, and said second portion including means for inverting the bits of the previous code by 1, and said second portion including means for inverting the bits of the previous code by 1 and adding these inverted bits to the delayed bits of previous code ay
 1. 